Circuit optimization is essential to perform power-performance trade-off. Most of the time, circuits are over-powered to meet timing (speed) constraints. This can be a big problem for high-performance chips for which there is increasingly important power limitations. Hence, most of the high-performance circuits are now becoming limited by power constraints. Although timing performance is still the primary target for integrated circuit (IC) manufacturers, power is recognized as the real performance limiter with current integration technologies. As devices shrink, they run faster at the expense of excessive leakage current. This poses itself as a tax on the performance, as the leakage power is becoming the dominant portion of the total power of a circuit, International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2004. Available at http://public.itrs.net. Hence power optimization must be performed at various stages of the design flow.
Circuit optimization research used to be concerned with automatically tuning the circuit solely for timing performance, and the transistor width used to be the primary variable to be continuously tuned. Established transistor sizing methodologies can be roughly divided into two categories. The first is sensitivity-based discrete heuristics represented by TILOS, which is described in J. P. Fishburn and A. E. Dunlop, TILOS: A Posynomial Programming Approach to Transistor Sizing, International Conference on Computer-Aided Design Digest of Technical Papers, pp. 326-328 (1985) and J. M. Shyu, A. Sangiovanni-Vincentelli, J. P. Fishburn and A. E. Dunlop, Optimization-Based Transistor Sizing, IEEE Journal of Solid Slate Circuits, vol. 23, no. 2, pp. 400-409 (1988). The transistor sizing operation is discretized, for example, a downsizing or upsizing operation can be defined as scaling the width of a transistor by a constant factor. The solution is optimal under certain simplistic delay f model, but suboptimal in general. The second is continuous nonlinear optimization, followed by snapping transistor sizes to the technology-imposed values as described in A. R. Conn, I. M. Elfadel, W. W. Molzen, P. R. O'Brien, P. N. Strenski, C. Visweswariah and C. B. Whan, Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation, Proceedings of Design Automation Conference, pp. 452-459 (1999). Because its solution in the continuous domain is optimal and transistor widths are near-continuous variables, the quality is typically superior to discrete heuristics, at the cost of high runtime.
With the advent of multiple-Vt devices, voltage islands and multiple oxide thickness, the list of candidate variables is now expanded by a number of discrete operations, e.g., as described in K. Fujii, T. Douseki and M. Harada, A Sub-IV Triple-Threshold CMOS/SIMOX Circuit for Active Power Reduction, International Solid-State Circuits Conference Digest of Technical Papers, pp. 190-191 (1998), which often offer better power-delay tradeoffs than transistor sizing. Most prominently, because sub-threshold leakage current is an exponential function of Vt, see L. Wei, K. Roy and C. Koh, Power Minimization by Simultaneous Dual-Vth Assignment and Gate-Sizing, Proceedings of IEEE Custom Integrated Circuits Conference, pp. 413-416 (2000), changing certain gates to higher Vt has the potential to achieve more power savings than gate sizing alone with the same timing budget. Recently gate-length is also suggested as a new design parameter, where it can be selected from a variety of alternatives as opposed to a single design length, P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, Gate-Length Biasing for Runtime Leakage Control, IEEE Transactions on Computer-Aided Design, pp. 1475-1485, August 2006.
Since the optimal solution is most likely achieved by the simultaneous consideration of all design options, various methods have been proposed to incorporate multiple operations. However, it is not trivial to incorporate discrete variables into a continuous sizing methodology, and the cost is often sub-optimality and significant runtime increase. Therefore, most of these multi-variable methods are heuristics and are often based on sensitivities defined similar to TILOS.